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  SiFive provides a complete portfolio of USB-certified controllers with host and device functionality. They are integrated with our partners in multiple foundries and nodes. MCU CSR interface , FPGA boards are available for demo and prototype use. ·          Compliant with USB 3.1 Gen 2 specification, USB 3.1 PIPE interface ·          Supports 32/64 data bus width ·          AXI, AHB bus standards ·          Supports 32/64/128 bit data bus ·          Supports all USB 3.1 power down modes ·          Supports Ccontrol, bulk, Iiochronous and interrupt transactions ·          Bulk endpoint support streaming ·          Device can be configurable up to 15 ...

  Integrated HBM controller and HBM PHY subsystem solution supporting HBM3, HBM2E and HBM2 JEDEC spec for a wide range of technology and foundry nodes. As an early advocate of 2.5D and 3D ASIC design technologies and by leveraging its experience from the industry’s first multiple successful 2.5D SoC SiP demonstration, OpenFive plays a key role in enabling industry applications that leverage the HBM 3D-stacked DRAM technology.   Die-to-Die IP Subsystem is targeted for heterogenous chiplet solutions in wired communications, AI and HPC applications. With recent advances in package technologies, it is possible to route high-speed signals within a package connecting multiple dies either on Interposer or on Organic Substrate. Die-to-Die Interposer I/O offers a unique value proposition in terms of low power, high throughput and low latency links enabling faster time to integration.   SiFive provides a complete portfolio of USB-certified controllers with host and device...

  High speed chip - to - chip interface protocol with scalable bandwidth, low latency and reliable data transfer over serial links. The latest generation supports up to 1.2Tbps bandwidth with support for NRZ and PAM4 serial links. Interlaken IP is used by many applications including NPU, traffic management and switch fabrics. Open-Silicon, a SiFive company, was a founding member of the Interlaken Alliance and supports silicon-proven Interlaken IP with over 75+ tier 1 customers on various technology and process nodes. The IP P ortfolio includes a validation platform supporting up to 1.2Tbps (64K channels and 48 SerDes lanes) using a wide range of transceiver speeds and Forward Error Correction (FEC) engines. Extending on the 8th generation of its Interlaken IP core, SiFive now introduces low latency version of the Chip-to-Chip and Die-to-Die connectivity Interlaken IP used across many applications. Cutting edge technologies such as High Performance Computing (HPC) cluster...