IP Portfolio-High speed chip-to-chip interface protocol
High
speed chip-to-chip interface protocol with scalable
bandwidth, low latency and reliable data transfer over serial links. The latest
generation supports up to 1.2Tbps bandwidth with support for NRZ and PAM4
serial links.
Interlaken IP is used by many applications
including NPU, traffic management and switch fabrics. Open-Silicon, a SiFive
company, was a founding member of the Interlaken Alliance and supports
silicon-proven Interlaken IP with over 75+ tier 1 customers on various
technology and process nodes. The IP Portfolio includes a validation platform supporting up
to 1.2Tbps (64K channels and 48 SerDes lanes) using a wide range of transceiver
speeds and Forward Error Correction (FEC) engines.
Extending on the 8th
generation of its Interlaken IP core, SiFive now introduces low latency version
of the Chip-to-Chip and Die-to-Die connectivity Interlaken IP used across many
applications. Cutting edge technologies such as High Performance Computing
(HPC) clusters, AI/ML chip clusters, IoT edge devices, networking, and
switching fabrics are demanding high throughput data transfer from one chip to
another at very low latency. Interlaken-LL includes a validation platform
supporting up to 256Gbps.
OpenFive, the leading provider
of customizable, silicon-focused solutions with differentiated IP, today
announced the launch of a new Die-to-Die (D2D) interface IP portfolio to serve
next-generation chipset based designs for Networking, HPC, and AI Markets.
With recent advances in package
technologies and the cost per area increase in newer nodes, it is advantageous
to connect multiple dies, or chiplets, on a single package with a silicon-based
interposer or an organic substrate. To enable this heterogeneous integration
for various markets, OpenFive Die-to-Die connectivity IP is a major enablement
block. OpenFive’s 1st Generation Die-to-Die IP is specifically designed to provide
a very low-latency controller to work with SerDes based connectivity between
two dies. OpenFive Die-to-Die IP is intended to enable SoC architects to
connect chip logic to optimized XSR/VSR/SR based SerDes while embracing native
customer-defined interfaces, or Arm® AMBA® AXI.
OpenFive’s die-to-die
controller uniquely offers low latency and scalable throughput to address very
high-bandwidth requirements in the multi terabits range with a single
controller. Optional low latency FEC (Forward Error Correction) IP Engines can
help achieve very low bit error rates (BER) depending on the characteristics of
the channel connecting the two dies.
“We have achieved a throughput
of up to >2Tbps and latency of few tens of nano-seconds end to end with a
lead customer in HPC,” said Mohit Gupta, SVP and General Manager, IP Business
Unit, OpenFive. “Additionally, working with our leading SerDes partners, we can
offer a complete sub-system solution optimized for their needs.”
OpenFive is uniquely positioned
with over a decade of experience in providing solutions for leading networking,
storage, and AI products with its Interlaken IP for Chip-to-Chip connectivity,
coupled with 2.5D-based ASIC integration experience for HBM2E based products.
OpenFive will continue to
extend the series of Die-to-Die IP portfolio for other parallel PHY based
architectures in the future as they become available.
OpenFive is a self-contained
and autonomous custom silicon business unit of SiFive and offers customizable
and differentiated SoC IP for Artificial Intelligence, Edge Computing, HPC, and
Networking solutions. The OpenFive portfolio includes low-latency,
high-throughput Interlaken connectivity fabric, 400/800G Ethernet,
High-bandwidth memory (HBM2/E), USB subsystem IP, and die-to-die interconnect
IP for next-generation heterogeneous chiplet-style products.
OpenFive’s end-to-end expertise
in Architecture, Design Implementation, Software, Silicon Validation, and
Manufacturing delivers high-quality silicon, with first-time-right results.
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