MCU CSR interface-SERDES interface-PHY with PIPE interface

 

SiFive provides a complete portfolio of USB-certified controllers with host and device functionality. They are integrated with our partners in multiple foundries and nodes. MCU CSR interface , FPGA boards are available for demo and prototype use.

·         Compliant with USB 3.1 Gen 2 specification, USB 3.1 PIPE interface

·         Supports 32/64 data bus width

·         AXI, AHB bus standards

·         Supports 32/64/128 bit data bus

·         Supports all USB 3.1 power down modes

·         Supports Ccontrol, bulk, Iiochronous and interrupt transactions

·         Bulk endpoint support streaming

·         Device can be configurable up to 15 IN and 15 OUT functional endpoints

·         Configurable number of function endpoints

·         Dynamically configurable endpoint FIFO for optimum usage of memory

·         Synchronous SRAM interface for FIFO

·         Fully integrated DMA controller

High Level Features

• Compliant to USB 3.1 Appendix E standard
• Supports Gen 1(5G) and Gen 2(10G) speeds
• Supports all low power states
• Supports MCU CSR interface to drive ASIC control and status register
• Supports PCS logic with 8b/10b for Gen1 and 128b/132b for Gen2 support
• Supports SERDES interface
• Optional support to external PHY with PIPE interface
• SRIS architecture
• “Pass through” and “local loopback” supported
• Provision to monitor key events including internal errors
• Provision to monitor link states
• Option to tune PIPE control signal through CSR interface
• Master loopback support for production test
• Option to generate LFPS pattern in debug mode

Integrated HBM controller and HBM PHY subsystem solution supporting HBM3, HBM2E and HBM2 JEDEC spec for a wide range of technology and foundry nodes. As an early advocate of 2.5D and 3D ASIC design technologies and by leveraging its experience from the industry’s first multiple successful 2.5D SoC SiP demonstration, OpenFive plays a key role in enabling industry applications that leverage the HBM 3D-stacked DRAM technology.

 

Die-to-Die IP Subsystem is targeted for heterogenous chiplet solutions in wired communications, AI and HPC applications. With recent advances in package technologies, it is possible to route high-speed signals within a package connecting multiple dies either on Interposer or on Organic Substrate. Die-to-Die Interposer I/O offers a unique value proposition in terms of low power, high throughput and low latency links enabling faster time to integration.

 

Die-to-Die Interposer I/O

 

·         CMOS I/O with programmable drive strengths

·         3.2 Gbps / 1.6 GHz DDR with light output loading

·         Up to 5mm interposer trace length support meeting > 3.2 Gbps per pin date rate

·         Electrically compatible with JEDEC HBM3/2E/2 spec

·         Low latency controller features

·         Optional differential receiver

D2D PHY IP Key Features

 

·         D2D PHY signals are single ended (Single Duplex) and are based on HBM Memory Electrical IOs

·         Each channel is made up of 42 pairs of Tx/Rx signals that runs at configurable speed up to 16Gbps contributing up to ~1.75Tbps/mm

·         Channel lengths support up to 5mm with latency less than 5ns (Other combinations are available)

·         Best in the industry less than 0.5 pJ/bit power consumption

·         Built-in PLL to support differential clock forwarding

·         Self-contained initialization and calibration state machines

·         No requirement of Forward Error Correction (FEC) IP as signal supports channel BER up to 1E-21

·         Programmable output drivers, compatible to various parallel wire specification in the industry.